¥49.00¶¨¼Û£º¥58.00 (8.45ÕÛ)
ASICÉè¼ÆÀíÂÛÓëʵ¼ù(RTLÑéÖ¤×ÛºÏÓë°æͼÉè¼Æ¸ßµÈѧУÐÅÏ¢¼¼ÊõÀàз½Ïòж¯ÄÜÐÂÐÎ̬ϵÁÐ
¥31.05¶¨¼Û£º¥45.00 (6.9ÕÛ)
ASICÉè¼ÆÀíÂÛÓëʵ¼ù(RTLÑéÖ¤×ÛºÏÓë°æͼÉè¼Æ¸ßµÈѧУÐÅÏ¢¼¼ÊõÀàз½Ïòж¯ÄÜÐÂÐÎ̬ϵÁÐ
¥31.95¶¨¼Û£º¥45.00 (7.1ÕÛ)
Ã÷ÐǵêÆÌ ²©¿âÍøÆì½¢µê
¡¾Ô¤¶©¡¿ASIC-Design: Realisierung Von VLSI-Systemen Mit Mentor V ÃÀ¹ú¿â·¿·¢»õ£¬Í¨³£¸¶¿îºó3-5Öܵ½»õ£¡
Product Details »ù±¾ÐÅÏ¢ ISBN-13 ÊéºÅ 9783540616641 Author ×÷Õß Hoppe, Bernhard(×÷Õß) Format °æ±¾ ƽװ-½º¶© Pages Number Ò³Êý 522Ò³ Publisher ³ö°æÉç Springer Publication Date ³ö°æÈÕÆÚ 1999-03-09 Product Dimensions ÉÌÆ·³ß´ç 9.2 x 6.1 x 1 cm Shipping Weight ÉÌÆ·ÖØÁ¿ 1650g Language ÓïÖÖ Ó¢Óï Book Contents ÄÚÈݼò½é Der unmittelbare Praxisbezug und die "learning by doing" -Strategie dieses Buches versetzt Studenten und Entwickler in der Industrie rasch in die Lage, ASICs mit professionellen Werkzeugen zu entwerfen. Es kombiniert eine allgemeine EinfA1/4hrung in die Entwurfmethodik und Realisier
¥648.00
ASICÉè¼ÆÀíÂÛÓëʵ¼ù(RTLÑéÖ¤×ÛºÏÓë°æͼÉè¼Æ¸ßµÈѧУÐÅÏ¢¼¼ÊõÀàз½Ïòж¯ÄÜÐÂÐÎ̬ϵÁÐ
¥31.05¶¨¼Û£º¥45.00 (6.9ÕÛ)
¥1175.25
¡¾Ô¤¶©¡¿ASIC/SoC Functional Design Verification: A Comprehensive ÃÀ¹ú¿â·¿·¢»õ£¬Í¨³£¸¶¿îºó3-5Öܵ½»õ£¡
Product Details »ù±¾ÐÅÏ¢ ISBN-13 ÊéºÅ 9783319866208 Format °æ±¾ ƽװ-½º¶© Publisher ³ö°æÉç Springer Publication Date ³ö°æÈÕÆÚ 2018-08-12 Language ÓïÖÖ Ó¢Óï Book Contents ÄÚÈݼò½é This book describes in detail all required technologies and methodologies needed to create a comprehensive, functional design verification strategy and environment to tackle the toughest job of guaranteeing first-pass working silicon. The author first outlines all of the verification sub-fields at a high level, with just enough depth to allow an engineer to grasp the field before delving into its detail. He then describes in detail industry standard technologies such as UVM (Universal Verification Methodology), SVA (SystemVerilog Assertions), SFC (SystemVerilog Functional Coverage), CDV (Coverage Driven Verification), Low Power Verification (Unified Power Format UPF), AMS (Analog Mixed Signal) verification, Virtual Platform TLM2.0/ESL (Electr
¥1022
¥31.90¶¨¼Û£º¥45.00 (7.09ÕÛ)
¡¾Ô¤¶©¡¿ASIC Synthesis Workshop ÃÀ¹ú¿â·¿·¢»õ£¬Í¨³£¸¶¿îºó3-5Öܵ½»õ£¡
¥1051
³¬ÉîÑÇ΢Ã×ʱ´ú¼¯³Éµç·Éè¼Æ·½·¨ÓëÉè¼Æ¹¤¾ßͨ¹ýÄ£¿é»¯ÊµÀýÀ´´òͨASICÉè¼Æ¸÷½×¶ÎÒªÁìÓÃÄ£¿é¼¯³ÉÀ´Íê³ÉÒ»¸öÍêÕûµÄCPUÉè¼ÆÔ´ÓÚ¶àÄê¿Î³Ìʵ¼ùµÄ»ýÀÛ£¬ÅàÑø¼¯³Éµç·Éè¼ÆÈ˲ţ¬ÊµÏÖÕæÕý¡°Öйúо¡±
¥29.40¶¨¼Û£º¥45.00 (6.54ÕÛ)
¡¾Ô¤¶©¡¿ASIC and FPGA Verification: A Guide to Component ÃÀ¹ú¿â·¿·¢»õ£¬Í¨³£¸¶¿îºó3-5Öܵ½»õ£¡
¥639.00
ASICÉè¼ÆÀíÂÛÓëʵ¼ù(RTLÑéÖ¤×ÛºÏÓë°æͼÉè¼Æ¸ßµÈѧУÐÅÏ¢¼¼ÊõÀàз½Ïòж¯ÄÜÐÂÐÎ̬ϵÁÐ
¥31.30¶¨¼Û£º¥45.00 (6.96ÕÛ)
¡¾Ô¤¶©¡¿ASIC System Design with VHDL: A Paradigm ÃÀ¹ú¿â·¿·¢»õ£¬Í¨³£¸¶¿îºó3-5Öܵ½»õ£¡
¥1002
¡¾Ô¤¶©¡¿ASIC Design in the Silicon Sandbox: A Complete Guide ÃÀ¹ú¿â·¿·¢»õ£¬Í¨³£¸¶¿îºó3-5Öܵ½»õ£¡
¥1076
¡¾Ô¤¶©¡¿ASIC Design and Synthesis 9789813346413 ÃÀ¹ú¿â·¿·¢»õ£¬Í¨³£¸¶¿îºó3-5Öܵ½»õ£¡
Product Details »ù±¾ÐÅÏ¢ ISBN-13 ÊéºÅ 9789813346413 Author ×÷Õß Taraate Format °æ±¾ ¾«×° Pages Number Ò³Êý 330Ò³ Publisher ³ö°æÉç Springer Berlin Heidelberg Publication Date ³ö°æÈÕÆÚ 2021-01-07 Language ÓïÖÖ Ó¢Óï Book Contents ÄÚÈݼò½é This book describes simple to complex ASIC design practical scenarios using Verilog.Itbuilds a story from the basic fundamentals of ASIC designs to advanced RTL design concepts using Verilog. Looking at current trends of miniaturization, thecontentsprovide practical information on the issues in ASIC design and synthesis using Synopsys DC and their solution. The book explains how to write efficient RTL using Verilog and how to improve design performance.Italso covers architecture design strategies, multiple clock domain designs, low-power design techniques, DFT, pre-layout STA and the overall ASIC design flow with case studies. The contents of this book will be usefu
¥1664
ASICÉè¼ÆÀíÂÛÓëʵ¼ù¡ª¡ªRTL ÑéÖ¤¡¢×ÛºÏÓë°æͼÉè¼Æ Áõö© 9787115507679 ÈËÃñÓʵç³ö°æÉç
¥46.40¶¨¼Û£º¥48.24 (9.62ÕÛ)
³¬ÉîÑÇ΢Ã×ʱ´ú¼¯³Éµç·Éè¼Æ·½·¨ÓëÉè¼Æ¹¤¾ßͨ¹ýÄ£¿é»¯ÊµÀýÀ´´òͨASICÉè¼Æ¸÷½×¶ÎÒªÁìÓÃÄ£¿é¼¯³ÉÀ´Íê³ÉÒ»¸öÍêÕûµÄCPUÉè¼ÆÔ´ÓÚ¶àÄê¿Î³Ìʵ¼ùµÄ»ýÀÛ£¬ÅàÑø¼¯³Éµç·Éè¼ÆÈ˲ţ¬ÊµÏÖÕæÕý¡°Öйúо¡±
¥28.98¶¨¼Û£º¥90.00 (3.22ÕÛ)
ASICÉè¼ÆÀíÂÛÓëʵ¼ù(RTLÑéÖ¤×ÛºÏÓë°æͼÉè¼Æ¸ßµÈѧУÐÅÏ¢¼¼ÊõÀàз½Ïòж¯ÄÜÐÂÐÎ̬ϵÁÐ
¥33.75¶¨¼Û£º¥45.00 (7.5ÕÛ)
¡¾Ô¤¶©¡¿ASIC Basics: Black & White Edition ÃÀ¹ú¿â·¿·¢»õ£¬Í¨³£¸¶¿îºó3-5Öܵ½»õ£¡
¥105.00
ASICÉè¼ÆÀíÂÛÓëʵ¼ù(RTLÑéÖ¤×ÛºÏÓë°æͼÉè¼Æ¸ßµÈѧУÐÅÏ¢¼¼ÊõÀàз½Ïòж¯ÄÜÐÂÐÎ̬ϵÁÐ
¥31.30¶¨¼Û£º¥45.00 (6.96ÕÛ)
¡¾Ô¤ÊÛ °´ÐèÓ¡Ë¢¡¿ASIC Synthesis Workshop
¥1136.45
¡¾Ô¤¶©¡¿ASIC/Soc Functional Design Verification: A Comprehensive ÃÀ¹ú¿â·¿·¢»õ£¬Í¨³£¸¶¿îºó3-5Öܵ½»õ£¡
¥1343
ASICÉè¼ÆÀíÂÛÓëʵ¼ù(RTLÑéÖ¤×ÛºÏÓë°æͼÉè¼Æ¸ßµÈѧУÐÅÏ¢¼¼ÊõÀàз½Ïòж¯ÄÜÐÂÐÎ̬ϵÁÐ
¥31.29¶¨¼Û£º¥45.00 (6.96ÕÛ)
¡¾Ô¤¶©¡¿ASIC Synthesis Workshop Ô¤¶©ÉÌÆ·£¬°´ÐèÓ¡Ë¢£¬ÐèÒª1-3¸öÔ·¢»õ£¬·ÇÖÊÁ¿ÎÊÌâ²»½ÓÊÜÍË»»»õ¡£
¥1084.82
ASICÉè¼ÆÀíÂÛÓëʵ¼ù(RTLÑéÖ¤×ÛºÏÓë°æͼÉè¼Æ¸ßµÈѧУÐÅÏ¢¼¼ÊõÀàз½Ïòж¯ÄÜÐÂÐÎ̬ϵÁÐ
¥31.05¶¨¼Û£º¥45.00 (6.9ÕÛ)
ASICÉè¼ÆÀíÂÛÓëʵ¼ù(RTLÑéÖ¤×ÛºÏÓë°æͼÉè¼Æ¸ßµÈѧУÐÅÏ¢¼¼ÊõÀàз½Ïòж¯ÄÜÐÂÐÎ̬ϵÁÐ
¥31.25¶¨¼Û£º¥45.00 (6.95ÕÛ)
ASICÉè¼ÆÀíÂÛÓëʵ¼ù(RTLÑéÖ¤×ÛºÏÓë°æͼÉè¼Æ¸ßµÈѧУÐÅÏ¢¼¼ÊõÀàз½Ïòж¯ÄÜÐÂÐÎ̬ϵÁÐ
¥31.20¶¨¼Û£º¥45.00 (6.94ÕÛ)
Ã÷ÐǵêÆÌ Ä¾¶âͼÊéרӪµê
ASICÉè¼ÆÀíÂÛÓëʵ¼ù¡ª¡ªRTL ÑéÖ¤¡¢×ÛºÏÓë°æͼÉè¼Æ
³¬ÉîÑÇ΢Ã×ʱ´ú¼¯³Éµç·Éè¼Æ·½·¨ÓëÉè¼Æ¹¤¾ßͨ¹ýÄ£¿é»¯ÊµÀýÀ´´òͨASICÉè¼Æ¸÷½×¶ÎÒªÁìÓÃÄ£¿é¼¯³ÉÀ´Íê³ÉÒ»¸öÍêÕûµÄCPUÉè¼ÆÔ´ÓÚ¶àÄê¿Î³Ìʵ¼ùµÄ»ýÀÛ£¬ÅàÑø¼¯³Éµç·Éè¼ÆÈ˲ţ¬ÊµÏÖÕæÕý Öйúо
¥32.90¶¨¼Û£º¥45.00 (7.32ÕÛ) µç×ÓÊ飺¥22.50
¡¾Ô¤¶©¡¿ASIC Design and Synthesis 9789813346444 ¹úÍâ¿â·¿·¢»õ£¬Í¨³£¸¶¿îºó3-5Öܵ½»õ£¡
Product Details »ù±¾ÐÅÏ¢ ISBN-13 ÊéºÅ 9789813346444 Author ×÷Õß Vaibbhav Taraate Format °æ±¾ ƽװ-½º¶© Pages Number Ò³Êý nullÒ³ Publisher ³ö°æÉç Springer Berlin Heidelberg Publication Date ³ö°æÈÕÆÚ 2022-01-07 Product Dimensions ÉÌÆ·³ß´ç 9.21 x 6.14 x 0.74 Shipping Weight ÉÌÆ·ÖØÁ¿ 1.09 Language ÓïÖÖ ÆäËü£¨º¬¶àÓ Book Contents ÄÚÈݼò½é This book describes simple to complex ASIC design practical scenarios using Verilog. It builds a story from the basic fundamentals of ASIC designs to advanced RTL design concepts using Verilog. Looking at current trends of miniaturization, the contents provide practical information on the issues in ASIC design and synthesis using Synopsys DC and their solution. The book explains how to write efficient RTL using Verilog and how to improve design performance. It also covers architecture design strategies, multiple clock domain designs,
¥1216
¡¾Ô¤ÊÛ °´ÐèÓ¡Ë¢¡¿ASIC Basics ±±¾©·¢»õ£¬¸¶¿îºó10ÌìÄÚ·¢»õ
¥88.05
ÔËËãµç·¼¯³É FPGA¡¢ASICÓëǶÈëϵͳ Synthesis Of Arithmetic Circuits Ó¢ÎÄÔ°æ Jean-PierreDeschamps
¥615.00
Ã÷ÐǵêÆÌ ÖлªÉÌÎñ½ø¿ÚͼÊéÆì½¢µê
°´ÐèÓ¡Ë¢ASIC Design for a Coherent Optical Receiver Dspu Ô¤¶©£¬Ô¤¼Æϵ¥ºó2-3ÖÜ×óÓÒ·¢»õ£¡
¥856.00
º£ÍâÖ±¶©ASIC Synthesis Workshop ¼¯³Éµç·×ۺϳµ¼ä
¥831.00
Ã÷ÐǵêÆÌ ÖлªÉÌÎñ½ø¿ÚͼÊéÆì½¢µê
¥2171.39
¡¾Ô¤¶©¡¿An ASIC Low Power Primer 9781489991508 ÃÀ¹ú¿â·¿·¢»õ£¬Í¨³£¸¶¿îºó3-5Öܵ½»õ£¡
¥895.00
º£ÍâÖ±¶©ASIC Design in the Silicon Sandbox: A Complete Guide to
¥1167
Ã÷ÐǵêÆÌ ÖлªÉÌÎñ½ø¿ÚͼÊéÆì½¢µê
°´ÐèÓ¡Ë¢ASIC Basics Ô¤¶©£¬Ô¤¼Æϵ¥ºó2-3ÖÜ×óÓÒ·¢»õ£¡
¥103.00
Ô¤¶© ASIC Design for a Coherent Optical Receiver Dspu 97838443 º£Íâ²Ö¿â·¢»õ,ͨ³£¸¶¿îºó4-9Öܵ½»õ£¡
ͼÊéÐÅÏ¢ ÊéºÅ£º 9783844304190 ×÷Õߣº Vijitha Rohana Herath ×°Ö¡£º ƽװ-½º¶© Ò³Êý£º 112Ò³ ³ö°æÉ磺 Omnium Gmbh & Co. Kg. ³ß´ç£º 0.9 x 0.6 x 22.8 cm ³ö°æÈÕÆÚ£º 2011-02-04 ÖØÁ¿£º 176g ÓïÖÖ£º ÆäËü£¨º¬¶àÓ ÄÚÈݼò½é The exponential growth of the internet traffic makes it
¥686.00
º£ÍâÖ±¶©ASIC Design for a Coherent Optical Receiver Dspu Ïà¸É¹â½ÓÊÕ»úD
¥541.00
Ã÷ÐǵêÆÌ ÖлªÉÌÎñ½ø¿ÚͼÊéÆì½¢µê
Ô¤¶© ASIC Basics 9781435719101 º£Íâ²Ö¿â·¢»õ,ͨ³£¸¶¿îºó4-9Öܵ½»õ£¡
ͼÊéÐÅÏ¢ ÊéºÅ£º 9781435719101 ×÷Õߣº Elaine Rhodes ×°Ö¡£º ƽװ-½º¶© Ò³Êý£º 56Ò³ ³ö°æÉ磺 Lulu Press ³ß´ç£º 22.9 x 15.2 x 22.8 cm ³ö°æÈÕÆÚ£º 2008-05-26 ÖØÁ¿£º 95g ÓïÖÖ£º ÆäËü£¨º¬¶àÓ ÄÚÈݼò½é ASIC BASICS teaches you what ASICs are, how they are manufactured, and how
¥93.00
º£ÍâÖ±¶©ASIC Design and Synthesis: Rtl Design Using Verilog ASIC
¥1250
Ã÷ÐǵêÆÌ ÖлªÉÌÎñ½ø¿ÚͼÊéÆì½¢µê
Ô¤¶© ASIC Synthesis Workshop 9783659339097 º£Íâ²Ö¿â·¢»õ,ͨ³£¸¶¿îºó4-9Öܵ½»õ£¡
ͼÊéÐÅÏ¢ ÊéºÅ£º 9783659339097 ×÷Õߣº Bhat Naagesh ×°Ö¡£º ƽװ-½º¶© Ò³Êý£º 232Ò³ ³ö°æÉ磺 Omnium Gmbh & Co. Kg. ³ß´ç£º 0.9 x 0.6 x 0.1 cm ³ö°æÈÕÆÚ£º 2013-02-03 ÖØÁ¿£º 1g ÓïÖÖ£º ÆäËü£¨º¬¶àÓ ÄÚÈݼò½é The term 'ASIC' stands for 'application-specific integrated circuit
¥1078
º£ÍâÖ±¶©ASIC Design and Synthesis ASICÉè¼ÆÓëºÏ³É
¥1731
Ã÷ÐǵêÆÌ ÖлªÉÌÎñ½ø¿ÚͼÊéÆì½¢µê
¥77.09¶¨¼Û£º¥164.38 (4.69ÕÛ)
ASICÉè¼Æ»ìºÏÐźż¯³Éµç·Éè¼ÆÖ¸ÄÏ¡¾Õý°æÊé¼®£¬Âú¶î¼õ¡¿ ¡¾ËÙ¿ª·¢Æ±£¬ÓÅÖÊÊÛºó£¬Ö§³Ö7ÌìÎÞÀíÓÉÍË»»¡¿
¥166.20¶¨¼Û£º¥463.50 (3.59ÕÛ)
ASICÉè¼Æ»ìºÏÐźż¯³Éµç·Éè¼ÆÖ¸ÄÏ¡¾Õý°æÊé¼®£¬Âú¶î¼õ¡¿ ¡¾ËÙ¿ª·¢Æ±£¬ÓÅÖÊÊÛºó£¬Ö§³Ö7ÌìÎÞÀíÓÉÍË»»¡¿
¡¶ASICÉè¼Æ:»ìºÏÐźż¯³Éµç·Éè¼ÆÖ¸ÄÏ¡·Êǵç×Ó¹¤³Ì¡¢¼¯³Éµç·Éè¼ÆµÈÁìÓòµÄ¼¼ÊõÈËÔ±ºÍÑо¿ÈËÔ±µÄ²Î¿¼Ê飬ҲÊǸߵÈԺУÏà¹ØרҵʦÉúÖØÒªµÄѧϰÓÃÊé¡£
¥166.20¶¨¼Û£º¥453.60 (3.67ÕÛ)
ASICÍ걸ָÄÏ¡¾Õý°æÊé¼®£¬Âú¶î¼õ¡¿ ¡¾ËÙ¿ª·¢Æ±£¬ÓÅÖÊÊÛºó£¬Ö§³Ö7ÌìÎÞÀíÓÉÍË»»¡¿
¥78.70¶¨¼Û£º¥288.50 (2.73ÕÛ)
ASICÉè¼ÆÀíÂÛÓëʵ¼ù¡ª¡ªRTL ÑéÖ¤¡¢×ÛºÏÓë°æͼÉè¼Æ
³¬ÉîÑÇ΢Ã×ʱ´ú¼¯³Éµç·Éè¼Æ·½·¨ÓëÉè¼Æ¹¤¾ßͨ¹ýÄ£¿é»¯ÊµÀýÀ´Í¨ASICÉè¼Æ¸÷½×¶ÎÒªÁìÓÃÄ£¿é¼¯³ÉÀ´Íê³ÉÒ»¸öÍêÕûµÄCPUÉè¼ÆÔ´ÓÚ¶àÄê¿Î³Ìʵ¼ùµÄ»ýÀÛ£¬ÅàÑø¼¯³Éµç·Éè¼ÆÈ˲ţ¬ÊµÏÖÕæÕý Öйúо
¥22.50
±¾ÊéµÚ2°æÃèÊöÁËʹÓÃSynopsys¹¤¾ß½øÐÐASICоƬ×ۺϡ¢ÎïÀí×ۺϡ¢ÐÎʽÑéÖ¤ºÍ¾²Ì¬Ê±Ðò·ÖÎöµÄиÅÄîºÍ¼¼Êõ£¬Í¬Ê±Õë¶ÔVDSM£¨³¬ÉîÑÇ΢Ã×£©¹¤ÒÕµÄÍêÕûASICÉè¼ÆÁ÷³ÌµÄÉè¼Æ·½·¨½øÐÐÁËÉîÈëµÄ̽ÌÖ¡£±¾ÊéµÄÖصãÊÇʹÓÃSynopsys¹¤¾ß½â¾ö¸÷ÖÖVDSMÎÊÌâµÄʵ¼ÊÓ¦Ó᣶ÁÕß½«ÏêϸÁ˽âÓÐЧ´¦Àí¸´ÔÓÑÇ΢Ã×ASICµÄÉè¼Æ·½·¨£¬ÆäÖصãÊÇHDLµÄ±àÂë·ç¸ñ¡¢×ۺϺÍÓÅ»¯¡¢¶¯Ì¬·ÂÕæ¡¢ÐÎʽÑéÖ¤¡¢DFTɨÃè²íÈë¡¢lmkstolayout¡¢ÎïÀí×ۺϺ;²Ì¬Ê±Ðò·ÖÎö¡£ÔÚÿ¸ö²½ÖèÖУ¬È·¶¨ÁËÉè¼ÆÁ÷³ÌÖÐÿһ²¿·ÖµÄÎÊÌ⣬²¢ÏêϸÃèÊöÁ˽â¾ö·½·¨¡£´ËÍ⣬¶Ô°üÀ¨ÓëʱÖÓÊ÷×ۺϺÍlinkst0layo[tµÈ°æͼÏà¹ØµÄÎÊÌâÒ²½øÐÐÁ˽ÏÏêϸµÄÂÛÊö¡£¶øÇÒ£¬±¾Ê黹¶ÔSynosys»ù±¾µÄ¹¤ÒÕ¿â¡¢HDL±àÂë·ç¸ñÒÔ¼°µÄ×ۺϽâ¾ö·½°¸½øÐÐÁËÉîÈë̽ÌÖ¡£±¾ÊéµÄ¶ÁÕ߶ÔÏóÊÇASICÉè¼Æ¹¤³ÌʦºÍÕýÔÚѧ¹ØÓÚASICоƬ×ÛºÏÒÔ¼°DFT¼¼ÊõµÄVLSI¿Î³ÌµÄ˶ʿÑо¿Éú¡£
¥289.50¶¨¼Û£º¥700.20 (4.14ÕÛ)
±¾ÊéµÚ2°æÃèÊöÁËʹÓÃSynopsys¹¤¾ß½øÐÐASICоƬ×ۺϡ¢ÎïÀí×ۺϡ¢ÐÎʽÑéÖ¤ºÍ¾²Ì¬Ê±Ðò·ÖÎöµÄиÅÄîºÍ¼¼Êõ£¬Í¬Ê±Õë¶ÔVDSM£¨³¬ÉîÑÇ΢Ã×£©¹¤ÒÕµÄÍêÕûASICÉè¼ÆÁ÷³ÌµÄÉè¼Æ·½·¨½øÐÐÁËÉîÈëµÄ̽ÌÖ¡£±¾ÊéµÄÖصãÊÇʹÓÃSynopsys¹¤¾ß½â¾ö¸÷ÖÖVDSMÎÊÌâµÄʵ¼ÊÓ¦Ó᣶ÁÕß½«ÏêϸÁ˽âÓÐЧ´¦Àí¸´ÔÓÑÇ΢Ã×ASICµÄÉè¼Æ·½·¨£¬ÆäÖصãÊÇHDLµÄ±àÂë·ç¸ñ¡¢×ۺϺÍÓÅ»¯¡¢¶¯Ì¬·ÂÕæ¡¢ÐÎʽÑéÖ¤¡¢DFTɨÃè²íÈë¡¢lmkstolayout¡¢ÎïÀí×ۺϺ;²Ì¬Ê±Ðò·ÖÎö¡£ÔÚÿ¸ö²½ÖèÖУ¬È·¶¨ÁËÉè¼ÆÁ÷³ÌÖÐÿһ²¿·ÖµÄÎÊÌ⣬²¢ÏêϸÃèÊöÁ˽â¾ö·½·¨¡£´ËÍ⣬¶Ô°üÀ¨ÓëʱÖÓÊ÷×ۺϺÍlinkst0layo[tµÈ°æͼÏà¹ØµÄÎÊÌâÒ²½øÐÐÁ˽ÏÏêϸµÄÂÛÊö¡£¶øÇÒ£¬±¾Ê黹¶ÔSynosys»ù±¾µÄ¹¤ÒÕ¿â¡¢HDL±àÂë·ç¸ñÒÔ¼°µÄ×ۺϽâ¾ö·½°¸½øÐÐÁËÉîÈë̽ÌÖ¡£±¾ÊéµÄ¶ÁÕ߶ÔÏóÊÇASICÉè¼Æ¹¤³ÌʦºÍÕýÔÚѧ¹ØÓÚASICоƬ×ÛºÏÒÔ¼°DFT¼¼ÊõµÄVLSI¿Î³ÌµÄ˶ʿÑо¿Éú¡£
¥289.50¶¨¼Û£º¥710.10 (4.08ÕÛ)
¡¾Ô¤¶©¡¿Advanced ASIC Chip Synthesis Using Synopsys Design ÃÀ¹ú¿â·¿·¢»õ£¬Í¨³£¸¶¿îºó3-5Öܵ½»õ£¡
¥2199
¡¾Ô¤¶©¡¿Advanced ASIC Chip Synthesis: Using Synopsys(r) Design C ÃÀ¹ú¿â·¿·¢»õ£¬Í¨³£¸¶¿îºó3-5Öܵ½»õ£¡
¥2199
Ô¤ÊÛ °´ÐèÓ¡Ë¢ ASIC Design for a Coherent Optical Receive ±±¾©·¢»õ£¬¸¶¿îºó10ÌìÄÚ·¢»õ
¥856.00
¡¾Ô¤¶©¡¿Advanced ASIC Chip Synthesis: Using Synopsys(r) Design C ÃÀ¹ú¿â·¿·¢»õ£¬Í¨³£¸¶¿îºó3-5Öܵ½»õ£¡
¥520.00
¥3392.9
º£ÍâÖ±¶©An ASIC Low Power Primer: Analysis, Techniques and Speci
¥1346
Ã÷ÐǵêÆÌ ÖлªÉÌÎñ½ø¿ÚͼÊéÆì½¢µê
º£ÍâÖ±¶©An ASIC Low Power Primer: Analysis, Techniques and Speci
¥961.00
Ã÷ÐǵêÆÌ ÖлªÉÌÎñ½ø¿ÚͼÊéÆì½¢µê
CPLD/FPGAÓëASICÉè¼Æʵ¼ù½Ì³Ì£¨µÚ¶þ°æ£© ³ÂØÓÖø
¥44.20¶¨¼Û£º¥65.00 (6.8ÕÛ)
¡¾Ô¤¶©¡¿Espace, temps, pr¨¦positions 9782600011969 ¹úÍâ¿â·¿·¢»õ£¬Í¨³£¸¶¿îºó3-5Öܵ½»õ£¡
Product Details »ù±¾ÐÅÏ¢ ISBN-13 ÊéºÅ 9782600011969 Author ×÷Õß Asic Format °æ±¾ ¾«×° Publisher ³ö°æÉç Droz Publication Date ³ö°æÈÕÆÚ 2008-01-25 Language ÓïÖÖ ÆäËü£¨º¬¶àÓ Book Contents ÄÚÈݼò½é Une ontologie spatio-temporelle qui permet de d¨¦finir de mani¨¨re formelle le s¨¦mantisme de base des pr¨¦positions spatiales, temporelles et spatio-temporelles en fran?ais.
¥1003
¥52.00¶¨¼Û£º¥65.00 (8ÕÛ)
Ã÷ÐǵêÆÌ ÎÄÐùÍøÆì½¢µê